Modern memory integrated circuits, particularly read/write circuits such as static random access memories (SRAMS) and dynamic random access memories (DRAMs), are becoming quite large in physical size and in the density of memory locations therein. For example, SRAMs with 2.sup.20 addressable locations and DRAMs with 2.sup.22 addressable locations are now readily available. Even with submicron feature sizes, the physical size of the integrated circuit chip containing such memories can be as large as on the order of 180 kmil.sup.2. In addition, many complex microprocessors now include significant amounts of on-chip memory, such as 64 kbytes or more of read-only memory and 64 kbytes or more of random access memory. The physical chip size of some of these modern microprocessors may be as large as on the order of 250 kmil.sup.2.
It is well known that as the minimum feature size in integrated circuit chips becomes smaller, the size of defect that can cause a failure (i.e., the size of a "killing" defect) also shrinks. As a result, especially with large chip sizes, it is more difficult to achieve adequate manufacturing yield as the size of a killing defect reduces. In order to reduce the vulnerability of a relatively large integrated circuit chip to a single small defect, modern integrated circuits utilize spare rows and columns that can be used to replace defective rows and columns, respectively, in the memory portion of the circuit. Substitution of one of the spare rows or columns is conventionally accomplished by the opening of fuses (or closing of antifuses, as the case may be) in decoder circuitry, so that access is made to the spare row or column upon receipt of the address for the defective row or column in the primary memory array. Conventional fuses include polysilicon fuses which can be opened by a laser beam, and also avalanche-type fuses and antifuses.
Examples of memory devices incorporating conventional redundancy schemes are described in Hardee, et al., "A Fault-Tolerant 30 ns/375 mW 16K.times.1 NMOS Static RAM", J. Solid State Circuits, Vol. SC-16, No. 5 (IEEE, 1981), pp. 435-43, and in Childs, et al., "An 18 ns 4K.times.4 CMOS SRAM", J. Solid State Circuits, Vol. SC-19, No. 5 (IEEE, 1984), pp. 545-51. An example of a conventional redundancy decoder is described in U.S. Pat. No. 4,573,146, issued Feb. 25, 1986, assigned to SGS-Thomson Microelectronics, Inc., and incorporated herein by this reference.
In most memories containing redundant elements, however, the time required to access a redundant memory cell is longer than that required to access a memory cell in the primary array. Accordingly, the worst case access time for the memory is generally degraded by the enabling of redundant elements. It has been observed that a significant portion of the access time degradation is due to additional delays in the decoders associated with the redundant elements, which compare the received address value against the programmed address value to which the redundant element is to respond (i.e., the address of the replaced primary array element). Especially where the chip size of the memory is sufficiently large, significant delay is also present in the mere propagation of address signals to the redundant decoders.
Furthermore, conventional memories that assign multiple redundant columns are associated with a single redundant sense amplifier (and write circuit) generally perform a logic function on the output of the redundant decoders to determine if any one of the multiple redundant columns are being selected and, if so, enabling the sense amplifier (or write circuit, as the case may be) responsive to such selection. This logic function, for example a summing by way of a NAND, also presents propagation in the critical timing path for accessing a redundant memory cell.
As a result, the access time for a redundant memory cell is generally slower than that for a primary memory cell, in many memories. Of course, access time specifications must be met by the worst case access condition, making such memories having redundant memory cells enabled slower than a non-repaired memory. This loss in performance can have an economic effect on the manufacturer, as higher speed memories command a price premium in the market place.
It is therefore an object of the present invention to provide a memory in which the access time push-out associated with the access of redundant memory cells is reduced or eliminated.
It is a further object of the present invention to provide such a memory in which the such improved accessibility of redundant memory cells without a significant power dissipation penalty.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.